Novel approach for cache memory simulation at approximately-timed TLM abstraction level for SMP system

Abstract

To meet the ever increasing high speed computing requirements of complex System on Chips (SoC), there has been an increasing trend towards adopting Symmetric Multiprocessing (SMP) Systems encapsulating multiple processing cores each having multi-level cache memory for faster accesses. At an early design phase, estimating the requirement of - cache memory size and levels, prefetching strategy, snooping mechanism and coherency protocol to be adopted may save a lot of RTL simulation time and SoC area. Also, optimized cache parameters facilitate better SoC performance in terms of Bandwidth, latency, FIFO depth, arbitration policies etc. of various IP cores. In this work, keeping above in view, a novel approach is proposed to simulate coherent (Multi-Level) Cache Memory based on MESI protocol for Multi-Core Symmetric Multiprocessing (SMP) System deploying the benefits of Timed TLM simulations at an early design phase. The proposed Cache Memory system is provided with the memory reference traces extracted from earlier SoC simulation. Based on the user requirement, a memory hierarchy is dynamically generated which produces various cache memory access statistics which can be appropriately used for optimizing Cache Memory parameters.