Design and Investigation of SRAM using Charge Plasma Dopingless Nanowire FET

Prateek Goel, Madan Gopal Agrawal, S. Anand, Pradeep Kumar, Leo Raj Solay
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Abstract

A static random-access memory (SRAM) using Charge Plasma Dopingless Nanowire Field Effect Transistor (CP-DLNWFET) with radius 5 nm and channel length of 20nm is proposed. With the FET devices, a problem in decreasing the channel length due to Short Channel Effects (SCEs) and as subthreshold swing (SS) can’t be decreased below 60mV/decade as below it there is an irregular variation between the current and voltage. To overcome these limitations, Nanowire device structure with charge plasma technique is proposed to achieve better current conditions for the implementation of SRAM circuit. The charge plasma technique with appropriate selection of work function for source/drain metal electrodes are induced in dopingless structure. Random dopant fluctuation effect is reduced with the help of dopingless devices with easier steps of fabrication using lower thermal budget. During the operation of the proposed SRAM using CP-DLNWFET device at $V_{\mathbf{DD}} =$ 1V, has achieved 9.96 % for write mode, 24.4 % for read mode and 22.3 % for standby mode proving its stability than previously proposed devices.
无电荷等离子体掺杂纳米线场效应管SRAM的设计与研究
提出了一种半径为5 nm、通道长度为20nm的无电荷等离子体掺杂纳米线场效应晶体管(CP-DLNWFET)静态随机存取存储器。对于FET器件,由于短通道效应(SCEs)和亚阈值摆幅(SS)不能降低到60mV/ 10以下,因此在减小通道长度方面存在一个问题,因为在60mV/ 10以下,电流和电压之间存在不规则变化。为了克服这些限制,提出了采用电荷等离子体技术的纳米线器件结构,为SRAM电路的实现提供了更好的电流条件。采用电荷等离子体技术对源极/漏极金属电极的功函数进行了适当的选择,诱导出了无掺杂结构。无掺杂器件的制造步骤更简单,热预算更低,减少了随机掺杂波动效应。在$V_{\mathbf{DD}} =$ 1V的电压下,采用CP-DLNWFET器件的SRAM在运行过程中,写入模式的利用率为9.96%,读取模式的利用率为24.4%,待机模式的利用率为22.3%,证明了该器件的稳定性。
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