Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms

Abstract

This paper presents hardware/software co-design architecture targeted on a single FPGA for two typical lattice decoding algorithms in MIMO system. Two levels of parallelisms are analyzed for an efficient implementation with the preprocessing part on embedded MicroBlaze soft processor and the decoder part on customized hardware. The system prototypes of the AV and VB decoders show that they support up to 34.2 Mbps and 3.15 Mbps data rate respectively on XUP Virtex-II pro developing board, which are 19 and 16 times faster than their respective implementations on a DSP