C. Dimarino, Wenli Zhang, Nidhi Haryani, Qiong Wang, R. Burgos, D. Boroyevich
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引用次数: 17
Abstract
This paper presents the design, fabrication and testing of a 1.2 kV, 90 A SiC MOSFET half-bridge module in synchronous configuration. The module has low gate- and power-loop parasitic inductances, and has more than twice the power density (127.8 W/in3), and less than half of the switching loss (1.3 mJ), as similarly-rated commercial half-bridge modules, while employing standard, cost-effective packaging materials and technologies. The design of a high-speed gate drive will also be presented. The gate drive includes an active Miller clamp, which suppresses the cross-talk between the MOSFETs in the half-bridge. The measured module efficiency is 99 % when operating in a dc-dc synchronous boost converter.