A 100–123GHz CMOS frequency doubler with 5.5dBm output power and high fundamental rejection

Abstract

This paper presents a frequency doubler that operates at W-band and D-band frequencies between 100GHz to 123GHz. An optimized buffering method is proposed to achieve saturated output power as high as 5.5dBm with over 60dBc rejection of the fundamental frequency at −8dBm input power. The overall circuit power consumption is 116mW. The doubler was designed and implemented using 65nm CMOS technology.