An Optimal Design Methodology of Ternary Logic in Iso-device Ternary CMOS

Abstract

Studies report the possibility of the end of scaling, which is the key engine that has led the era of binary computers. Ternary computing is reported to have one of the highest potential to replace binary computers in the near future. Regarding this forecast, ternary CMOS (T-CMOS) is a device said to be a great candidate. However, research on actual circuit design must follow to verify its advantages fully. Thus, this paper studies the methodologies to design actual ternary logic based on T-CM OS devices. On top of the various novel ternary logic cells that we design, we propose an optimization technique to design arbitrary ternary logic with a minimum number of T-CMOS devices. Enlightening the usefulness of T-CMOS, we implemented a balanced ternary adder using only 68 transistors. Comparing between iso-device designs, we highlight that our ternary adder uses -30.6% fewer transistors than the most compact ternary adder currently-developed.