A linear-array WSI architecture for improved yield and performance

Abstract

A new architecture is proposed for constructing a linear array from cells on a partially defective wafer. Each cell connects to its four nearest neighbors in a way that guarantees a fixed delay between any pair of communicating cells. Phase-shifted synchronous clocking further improves performance. A simple configuration scheme is presented, and is shown to exceed 96% harvest of working cells when the configuration logic yield is above 75%. The architecture is shown to compare favorably to existing schemes in terms of performance, yield and overhead.<>