Hold time closure for subthreshold circuits using a two-phase, latch based timing method

Abstract

This paper presents an ultra low power (ULP) solution to hold time closure for subthreshold circuits across PVT variation and mismatch using a two-phase, latch based timing method. We show that compared to conventional hold buffering, our solution saves up to 37% (at 6σ yield) in energy per operation and allows for post tapeout hold time correction. Replacing registers with latches also permits time borrowing, which we show can save up to 47% (6σ yield) when used for setup time closure.