{"title":"Real-time benchmark set synthesis based on pWCET estimation and bounded hyper-periods","authors":"Ashraf Suyyagh, Z. Zilic","doi":"10.1109/CIRSYSSIM.2017.8023196","DOIUrl":null,"url":null,"abstract":"In evaluating performance, schedulability, and energy efficiency metrics for real-time systems, numerous algorithms have been proposed to construct synthetic tasksets for simulation. The resulting taskset characteristics should ideally reflect real workloads while the algorithms generating these tasksets should be efficient. Any experimentation using these tasksets will highly depend on their properties. Current approaches construct the sets by choosing taskset periods and utilisation from statistical distributions and compute the task worst case execution times accordingly. Tasks are generated through timed loops or matrix operations up to the specified task WCET. At times, the taskset hyper-period is bounded to minimise simulation interval through selected assignment of task periods. However, tasks which burn processor cycles through loops and matrix operations do not always reflect realistic task loads. In this paper, we propose a methodology for generating realistic tasksets based on available embedded benchmarks. We extend on previous work and propose new algorithms: CPA-AU/DU (Compute-Propagate-Adjust Ascending/Descending Utilisation) which efficiently pair taskset WCETs with selected discrete periods. Our tasksets have bounded and feasible simulation interval and meet desired total utilisation with minimum digression errors. We also show that our algorithms run in polynomial time.","PeriodicalId":342041,"journal":{"name":"2017 International Conference on Circuits, System and Simulation (ICCSS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Circuits, System and Simulation (ICCSS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CIRSYSSIM.2017.8023196","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In evaluating performance, schedulability, and energy efficiency metrics for real-time systems, numerous algorithms have been proposed to construct synthetic tasksets for simulation. The resulting taskset characteristics should ideally reflect real workloads while the algorithms generating these tasksets should be efficient. Any experimentation using these tasksets will highly depend on their properties. Current approaches construct the sets by choosing taskset periods and utilisation from statistical distributions and compute the task worst case execution times accordingly. Tasks are generated through timed loops or matrix operations up to the specified task WCET. At times, the taskset hyper-period is bounded to minimise simulation interval through selected assignment of task periods. However, tasks which burn processor cycles through loops and matrix operations do not always reflect realistic task loads. In this paper, we propose a methodology for generating realistic tasksets based on available embedded benchmarks. We extend on previous work and propose new algorithms: CPA-AU/DU (Compute-Propagate-Adjust Ascending/Descending Utilisation) which efficiently pair taskset WCETs with selected discrete periods. Our tasksets have bounded and feasible simulation interval and meet desired total utilisation with minimum digression errors. We also show that our algorithms run in polynomial time.