Electrical properties of p- and n-type silicon nanowires

Abstract

There has been considerable interest in bottom-up integration of semiconductor nanowires for their application in future logic, memory, and sensor circuits. The ability to integrate field effect devices with p- and n-type conduction channels is a challenge that must be overcome to fabricate complementary logic circuits using such technologies. In this talk, we present the results of four-point resistivity and gate-dependent conductance measurements taken on unintentionally-doped, p-type, and n-type silicon nanowires (SiNWs). These results emphasize that future efforts must address the source of the high p-type background doping concentration in vapor-liquid-solid grown SiNWs to facilitate improvements in the properties of n-channel devices.