A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link

Abstract

This paper presents a 65nm, 256 kbit SRAM memory which achieves both ultra low leakage power and very low active energy consumption at a speed of 850 MHz. Used techniques include divided word and bitlines, local write sense amplifiers, dynamic cell stability and a distributed decoder. In addition, three novel techniques are proposed which decrease power consumption even further. High threshold voltage cells reduce leakage and improve stability. Dual swing signalling on the global bitlines reduces energy without compromising robustness. The decoder uses a new type of dynamic gate to increase speed. The design was fabricated in a low power 65nm CMOS process. Measured performance for this 256 kbit SRAM with 32 bit wordlength is 4.3pJ per access and 25.2 μW leakage power at a speed of 850 MHz.