40 V BiCMOS technology with polysilicon emitter structure

Abstract

This paper describes a high voltage BiCMOS fabrication technique consisting of a selfaligned emitter process that uses reflowing PSG, photoetchs emitter contact windows and diffuses phosphorus in the windows through polysilicon. We also used a more lightly doped drain for NMOS transistors. As a result, we could fabricate bipolar transistors of over 40 V BV CEO and 1.56 GHz cutoff frequency ( fr ) and CMOS transistors of over 20 V BVDs.