Modeling and Characterization of Bias Stress-Induced Instability of SiC MOSFETs

Abstract

Threshold voltage instability due to bias stressing has been observed in SiC MOSFETs. Stressing at high gate bias has caused shifts up to several hundred millivolts in the threshold voltage of SiC MOSFETs which can significantly affect circuit performance. We have tried to characterize this threshold voltage instability by experimental and numerical modeling analyses. We see appreciable instability for stress times as less as 10s and stress voltages as low as 4V. Comparison of experiment and simulation indicates that this threshold voltage instability is caused due to excess oxide trapped charge, and also that the instability is reversible