Clock mesh framework

Abstract

Clock mesh network as an on-chip variation (OCV) tolerant design solution is a well known technique but is used only in high-end designs because of more resource requirements and complex synthesis techniques involved compared to traditional clock tree based solution. With shrinking technology nodes, the effects of OCV has become a major hurdle in achieving timing closure. In advanced nodes there is relatively more chip area available. Clock mesh is the preferred technology for a high fanout clock distributed over a large physical area. Mesh technologies lower the adverse impact of guard-banding, which in conventional CTS leads to lower performance. Since clock mesh is not used predominantly in mainstream designs, an automatic and robust solution is missing in existing physical design automation tools for its synthesis. The available mesh solutions are tedious and manual in general and require several atomic steps to achieve the required structure and performance. One more challenge with a manual clock mesh flow is the strict requirement of engineering expertise to design the best clock mesh configuration and to perform its analysis. In this paper we present a semi-automatic clock mesh synthesis framework which addresses the above mentioned problems. This automated solution offers a minimal number of steps with which one can design a robust clock mesh network. The framework also includes mesh planning tools which can aid the designer in choosing the best mesh configuration and thus lowering the experience requirement. Solutions to common practical issues faced such as blockages, macros, rectilinear floorplan and hierarchical design are also discussed. This framework is fully functional in a leading industry standard physical design automation tool. Across various industry standard ASIC designs, with this solution we consistently achieved skew that is less than one-third of the skew obtained by conventional clock-tree synthesis. With our clock-mesh methodology, we could also restrict on-chip skew variation to 5% compared to 20%-25% achievable in clock-tree synthesis.