Simulation of vertical channel nanoscale MOSFETs for low leakage DRAM cell

Abstract

A vertical channel nanoscale MOSFET for low leakage dynamic random access memory (DRAM) cell is proposed. Due to longer channel length than that of the conventional planner structure, the vertical channel structure can dramatically reduce short channel effect (SCE). This structure features a source extension to enhance subthreshold swing (SS), and a neck sidewall spacer to reduce gate induced drain leakage (GIDL).