Design of High-Speed Nanoscale Adder Logic Circuit for Low Power Consumption

Abstract

This This paper analyses the full Adder with different logic with 20 Transistors and the Full Adder with a different logic and the Buffer with 26 Transistors. The power calculations are done among the Full Adder with different logic (i.e.) average power, Power Leakage and power delay. Analyzing the power calculations of Full Adder with different Logic using 20 Transistors has the lowest delay power than the Full Adder with different logic with Buffer using 26 Transistors. The 4 Bit Ripple Carry Adder is the lowest Delay Power. Due to its low delay power and the efficiency of the 4 Bit Ripple Carry Adder using 20T, the simulation results are performed in the Virtuoso software cadence. The Model based on technology for the 180-nm CMOS process. This suggests that the proposed design have a higher speed than the other complete Adder designs.