{"title":"A digital frequency synthesizer for a 2.4 GHz fast frequency hopping transceiver","authors":"R. Uusikartano, J. Niittylahti","doi":"10.1109/MWSCAS.2000.951673","DOIUrl":null,"url":null,"abstract":"In this paper, a compact architecture of a digital frequency synthesizer for a 2.4 GHz fast frequency hopping radio modem is presented. The synthesizer is designed for generating 12-bit quadrature carrier signals from 50 to 90 MHz in 500 kHz steps. The phase-to-amplitude conversion is performed with a look-up table which is compressed by using the fact that only a limited set of discrete frequencies is needed. Simulation and synthesis results for a VHDL-implementation of the architecture are given. In addition, the proposed architecture is compared to a traditional look-up based direct digital frequency synthesizer with similar performance.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2000.951673","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper, a compact architecture of a digital frequency synthesizer for a 2.4 GHz fast frequency hopping radio modem is presented. The synthesizer is designed for generating 12-bit quadrature carrier signals from 50 to 90 MHz in 500 kHz steps. The phase-to-amplitude conversion is performed with a look-up table which is compressed by using the fact that only a limited set of discrete frequencies is needed. Simulation and synthesis results for a VHDL-implementation of the architecture are given. In addition, the proposed architecture is compared to a traditional look-up based direct digital frequency synthesizer with similar performance.