{"title":"Implementation of Close-Loop Control for Interleaved CrM Totem-Pole PFC Converters with GaN Devices","authors":"Jingjin Li, Zijian Chen, Siliang Zhang, Xinke Wu","doi":"10.1109/PEDG56097.2023.10215217","DOIUrl":null,"url":null,"abstract":"This paper presents a novel digital interleaving control method for GaN device-based two-phase interleaved totem-pole power factor correction (PFC) operating at the critical conduction mode (CrM) to overcome the challenges in achieving interleaving control in CrM PFC. The main objective of this study is to analyze the phase-locked-loop (PLL) control process in voltage-mode-controlled CrM PFC, establish the relationship between phase error and adjustment, and propose a method to design PLL parameters for digital implementation of interleaved CrM PFC converters. The experimental results were obtained from a 3600 W interleaved CrM totem-pole boost PFC prototype circuit, which was digitally controlled using a master-slave and PLL-based closed-loop.","PeriodicalId":386920,"journal":{"name":"2023 IEEE 14th International Symposium on Power Electronics for Distributed Generation Systems (PEDG)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE 14th International Symposium on Power Electronics for Distributed Generation Systems (PEDG)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PEDG56097.2023.10215217","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a novel digital interleaving control method for GaN device-based two-phase interleaved totem-pole power factor correction (PFC) operating at the critical conduction mode (CrM) to overcome the challenges in achieving interleaving control in CrM PFC. The main objective of this study is to analyze the phase-locked-loop (PLL) control process in voltage-mode-controlled CrM PFC, establish the relationship between phase error and adjustment, and propose a method to design PLL parameters for digital implementation of interleaved CrM PFC converters. The experimental results were obtained from a 3600 W interleaved CrM totem-pole boost PFC prototype circuit, which was digitally controlled using a master-slave and PLL-based closed-loop.