Simultaneous cycle-time reduction and output enhancement in a fully loaded foundry wafer fab

Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI:10.1109/ISSM.2000.993617

C. M. Ho, T. Chen, P. Hseih, C. Chu, E. Houn, K. J. Su, P. Wang, W. C. Yew, S.W. Sun

引用次数: 3

Abstract

A case study is reported in how cycle-time reduction and output enhancement were accomplished simultaneously in a fully loaded foundry wafer fab. Within one-year period of time, a 50 K per month capacity 6" foundry fab improved its overall cycle-time by 35% with a concurrent fab wafer-output increase of over 20%. In the mean time, the fab WIP level was reduced by more than 20% without any compromise in line-yield or customer delivery.

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在满负荷的晶圆厂中同时缩短周期和提高产量

本文报道了在一个满载的晶圆厂中如何同时实现缩短周期和提高产量的案例研究。在一年的时间里，一个每月50 K产能的6英寸晶圆代工厂将其整体周期时间缩短了35%，同时晶圆产量增加了20%以上。与此同时，晶圆厂的在制品水平降低了20%以上，而生产线良率和客户交货期没有任何影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)

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