A layout advisor for timing-critical bus routing

Abstract

We describe a "topology advisor" for routing of critical (multisource) buses in building-block design. The tool accepts as input a block layout, a two-layer routing cost structure superposed over the block layout, terminal locations for a multi-source bus, and source-sink delay upper bound (linear or Elmore delay) constraints for all terminal pairs. The b best routing solutions (b a user parameter) that satisfy all constraints are returned. Efficient implementations of exhaustive search are used to guarantee optimal results when practical, and otherwise yield fast, high-quality results (if the problem is large or if the constraints are loose). Practical features include: (i) modeling of per-region and per-layer routing costs, (ii) routing to terminals located inside blocks, (iii) optional splitting of k-pin bus routes when the optimal routing passes through narrow channels, and (iv) heuristic speedups based on clustering and sampling.