{"title":"Regenerative comparator with floating capacitor for energy-harvesting applications","authors":"Hadi Pahlavanzadeh, Mohammad Azim Karami","doi":"10.1049/cds2.12073","DOIUrl":null,"url":null,"abstract":"<p>An energy-efficient regenerative comparator design is unveiled. A floating capacitor is utilized to protect the complete discharge of the preamplifier output nodes by NMOS input transistors. The introduced floating capacitor is flipped around the preamplifier to allow PMOS cross-couple transistor charge reutilization and elevate amplification gain at the integration phase. By increasing amplification gain, the input common mode voltage of the NMOS latch that is toggled within some delay is increased, too. Therefore, the latch stage is activated strongly, and regeneration delay is reduced. Simulation results corroborate that the proposed technique reduces power consumption and input-referred offset by more than 60% compared with results of similar previous works. Furthermore, the referred noise and delay are improved more than 30%.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"15 8","pages":"842-851"},"PeriodicalIF":1.0000,"publicationDate":"2021-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12073","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Iet Circuits Devices & Systems","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/cds2.12073","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 3
Abstract
An energy-efficient regenerative comparator design is unveiled. A floating capacitor is utilized to protect the complete discharge of the preamplifier output nodes by NMOS input transistors. The introduced floating capacitor is flipped around the preamplifier to allow PMOS cross-couple transistor charge reutilization and elevate amplification gain at the integration phase. By increasing amplification gain, the input common mode voltage of the NMOS latch that is toggled within some delay is increased, too. Therefore, the latch stage is activated strongly, and regeneration delay is reduced. Simulation results corroborate that the proposed technique reduces power consumption and input-referred offset by more than 60% compared with results of similar previous works. Furthermore, the referred noise and delay are improved more than 30%.
期刊介绍:
IET Circuits, Devices & Systems covers the following topics:
Circuit theory and design, circuit analysis and simulation, computer aided design
Filters (analogue and switched capacitor)
Circuit implementations, cells and architectures for integration including VLSI
Testability, fault tolerant design, minimisation of circuits and CAD for VLSI
Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs
Device and process characterisation, device parameter extraction schemes
Mathematics of circuits and systems theory
Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers