An effective approach for hardware design of intra prediction in H.264/AVC

Abstract

In H.264/AVC standard, intra prediction is a key technology. In this paper, a novel finite-state machine for system control and a parallel architecture with four pixels parallelism for accelerating the predicted pixel calculation are proposed. Based on the location of sub-blocks, A few candidate modes are chosen for predicted pixel calculation, which adopts a configurable circuit for reduce the complexity of algorithm implement. With the analysis of the timing schedule in a macro block, a three-stage MB-pipelining architecture is applied to reduce the latency for intra prediction, which is the bottleneck of intra prediction. The proposed architecture is implemented in VHDL, and the VHDL code is verified to work at 100 MHz in a Xilinx Virtex-II Pro FPGA. The synthesis results show that the proposed architecture can completely satisfy the requirement of video encoding in the H.264 baseline profile standard.