A high-density 300 ps BiCMOS GRA

Abstract

A multiport BiCMOS embedded static RAM (SRAM) is introduced for use as a growable register array (GRA) in high-performance gate array technologies. This design provides read access times equivalent to those of bipolar RAMs, while maintaining soft-error rates that are lower than those of CMOS. Read access times of 300 ps were achieved by eliminating all emitter-coupled-logic (ECL) to CMOS conversion from the read paths. The current implementation allows array densities as high as 200 kb embedded in gate array logic.<>