Smart power mixed ICs parasitic bipolar coupling issues analysis with a dedicated on-chip sensor

Abstract

The presence of low power and high voltage devices in Smart Power integrated circuits (ICs) cause parasitic substrate interaction between switched power stages and sensitive analog blocks. This in turn is the major cause of failure of Smart Power ICs, inducing costly circuit redesign. In order to predict these harmful events, there is a need in IC industry to create a link between circuit designs, modelling and implementation in innovative software tools. Thus there is a real need to validate these new SPICE models by measuring the high voltage perturbations that activate parasitic structures in the substrate directly on the chip. This paper presents an analysis of parasitic bipolar coupling issues in Smart Power Mixed ICs with a dedicated on-chip sensor. The possible scenarios based on PNP and NPN activation are derived and a real life test vehicle is introduced and investigated in detail. For verification purposes multiple of the developed on-chip sensors are placed close to the expected sensitive nodes. The architecture and the capabilities of the sensor like multiplexing, sensitivity and the calibration possibility are explained in detail. The on-chip sensor is used as an on-chip oscilloscope to measure the transient voltage fluctuations induced by high voltage activity and coupled by the substrate. The test vehicle was developed and produced in ams HV CMOS technology.