S. Bai, Qian Liu, Kartheek Nalla, Jing Li, J. Drewniak, S. Connor, M. Cracraft, Bruce Archambeaul
{"title":"An EMI estimation for shielding edge treaments on a printed circuit board","authors":"S. Bai, Qian Liu, Kartheek Nalla, Jing Li, J. Drewniak, S. Connor, M. Cracraft, Bruce Archambeaul","doi":"10.1109/ISEMC.2016.7571722","DOIUrl":null,"url":null,"abstract":"Various PCB edge treatments including via stitching and edge plating connecting ground planes can be employed to suppress the EMI from multilayer printed circuit boards. The shielding performance of these edge treatments is studied in this work. Design curves and an empirical equation are given based on parametric study to summarize the variation of the total radiated power (TRP) as a function of slot length (spacing between vias) and number of openings. Comparisons between measurements and simulation suitably agree within engineering accuracy.","PeriodicalId":326016,"journal":{"name":"2016 IEEE International Symposium on Electromagnetic Compatibility (EMC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Symposium on Electromagnetic Compatibility (EMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISEMC.2016.7571722","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Various PCB edge treatments including via stitching and edge plating connecting ground planes can be employed to suppress the EMI from multilayer printed circuit boards. The shielding performance of these edge treatments is studied in this work. Design curves and an empirical equation are given based on parametric study to summarize the variation of the total radiated power (TRP) as a function of slot length (spacing between vias) and number of openings. Comparisons between measurements and simulation suitably agree within engineering accuracy.