Design Analysis and Comparative Study of GDI Based Full Adder Design

Abstract

In this paper, a 1-bit full adder is implemented using the Gate-Diffusion-Input (GDI) technique and its design analysis is carried out. The design parameters such as delay, power consumption, energy delay product, energy and transistor count are compared with the conventional static CMOS based design. The effect of parasitic capacitance is analyzed via post layout simulation. This reveals that the delay and power consumption of the GDI adder is around 19% and 94% less than to that of CMOS based approach along with reduced number of transistor count.