{"title":"Asynchronous High-Speed Combination Logic Circuitry using LTPS-TFT and BST for LCD Panel","authors":"T. Sato, Y. Suzuki, Y. Suga","doi":"10.1109/ISCIT.2008.4700179","DOIUrl":null,"url":null,"abstract":"In this paper, an asynchronous high-speed logic circuitry using low temperature poly silicon-thin film transistor (LTPS-TFT) and the bootstrapped technology (BST) for liquid crystal display (LCD) is proposed. The proposed logic circuit operates at high frequency region owing to the deep non-saturation operation by using the bootstrapped technology. To confirm some characteristics of the proposed circuit, an inverter and a NAND gate circuits are simulated. As the results, the power delay products are about 1/3 times less value than that of the conventional circuit under the conditions of +10 V power supply voltage and 0.5 pF load capacitor.","PeriodicalId":215340,"journal":{"name":"2008 International Symposium on Communications and Information Technologies","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International Symposium on Communications and Information Technologies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCIT.2008.4700179","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, an asynchronous high-speed logic circuitry using low temperature poly silicon-thin film transistor (LTPS-TFT) and the bootstrapped technology (BST) for liquid crystal display (LCD) is proposed. The proposed logic circuit operates at high frequency region owing to the deep non-saturation operation by using the bootstrapped technology. To confirm some characteristics of the proposed circuit, an inverter and a NAND gate circuits are simulated. As the results, the power delay products are about 1/3 times less value than that of the conventional circuit under the conditions of +10 V power supply voltage and 0.5 pF load capacitor.