Molded chip scale package for high pin count

S. Baba, Y. Tomita, M. Matsuo, H. Matsushima, N. Ueda, O. Nakagawa
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引用次数: 27

Abstract

A unique molded Chip Scale Package (CSP) associated 1024 pin counts has been developed. The design and process have been optimized in order to achieve high mount density, enhanced electrical characteristic and cost competitiveness. Also, the reliability testing was performed on thermal cycling and moisture induced crack resistivity. Finally, enhanced electrical and thermal characteristics were calculated.
模制芯片规模封装高引脚计数
一个独特的模压芯片规模封装(CSP)相关的1024引脚计数已开发。设计和工艺已经过优化,以实现高安装密度,增强电气特性和成本竞争力。并进行了热循环和湿致裂纹电阻率的可靠性试验。最后,计算了增强的电学和热特性。
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