New observations on hot carrier induced dynamic variation in nano-scaled SiON/poly, HK/MG and FinFET devices based on on-the-fly HCI technique: The role of single trap induced degradation

Abstract

In this paper, HCI induced dynamic variation in nano-scaled MOSFETs is systematically studied. Based on the proposed on-the-fly HCI technique, individual defect related HCI variation in small area device is observed for the first time. The fundamental properties of HCI variation sources (single trap induced degradation and trap number) are further investigated. The results show universal scaling trend for all the SiON/Poly, HK/MG and FinFET devices which confirms that the device dimension scaling is the dominant factor for the enhanced individual trap effect. Based on the new observations, HCI variation model is further discussed for the accurate prediction for design. Moreover, HCI variation is compared with BTI and RTN in terms of individual trap. The results show that HCI effect has the largest single trap impacts, which implies the defects responsible for HCI could be closer to dielectric-silicon interface than that for BTI and RTN.