R. Goldman, K. Bartleson, T. Wood, K. Kranen, C. Cao, Vazgen Melikyan, G. Markosyan
{"title":"Synopsys' open educational design kit: Capabilities, deployment and future","authors":"R. Goldman, K. Bartleson, T. Wood, K. Kranen, C. Cao, Vazgen Melikyan, G. Markosyan","doi":"10.1109/MSE.2009.5270840","DOIUrl":null,"url":null,"abstract":"An open Educational Design Kit (EDK) which supports a 90nm design flow is described which includes all the necessary design rules, models, technology files, verification and extraction command decks, scripts, symbol libraries, and PCells. It also includes a Digital Standard Cell Library (DSCL) which supports all contemporary low power design techniques; an I/O Standard Cell Library (IOSCL); a set of memories (SOM) with different word and data depths; and a phase-locked loop (PLL). These components of the EDK augment any type of design for educational and research purposes. Though the EDK does not contain any foundry information, it allows real 90nm technology with high accuracy to be implemented in the designs.","PeriodicalId":241566,"journal":{"name":"2009 IEEE International Conference on Microelectronic Systems Education","volume":"430 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"59","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International Conference on Microelectronic Systems Education","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MSE.2009.5270840","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 59
Abstract
An open Educational Design Kit (EDK) which supports a 90nm design flow is described which includes all the necessary design rules, models, technology files, verification and extraction command decks, scripts, symbol libraries, and PCells. It also includes a Digital Standard Cell Library (DSCL) which supports all contemporary low power design techniques; an I/O Standard Cell Library (IOSCL); a set of memories (SOM) with different word and data depths; and a phase-locked loop (PLL). These components of the EDK augment any type of design for educational and research purposes. Though the EDK does not contain any foundry information, it allows real 90nm technology with high accuracy to be implemented in the designs.