Engaging undergraduate students in nano-scale circuit research using summer internship

H. Mahmoodi, J. Garcia, J. Lohse, J. Paulino, H. Prado, A. Balani, S. Lakshmipuram, Cheng Chen, A. Enriquez, Hao Jiang, W. Pong, H. Shanasser
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Abstract

Semiconductor technology has been scaling at a steady pace following Moore's law. The current generations of the technology have reached dimensions well below 100nm where nano-scale phenomena are prominent. Transistors in such a small scale behave very differently than the classic long channel devices taught in most undergraduate level textbooks. Moreover, there are new challenges in nano-scale circuit design, such as process variations and reliability issues that are not taught in undergraduate level courses. Working on latest technology issues is typically an opportunity available only to graduate level students working on related research projects. To address this gap, using a NASA Curriculum Improvements Partnership Award for the Integration of Research (CIPAIR) grant, we have created a summer internship program that engages community college students in research projects on the latest challenges of circuit design in nano-scale semiconductor technology. Through this program, four community college students were mentored by two graduate students in a research project to analyze performance degradation of integrated circuits due to transistor aging effects in nano-scale. In this research, analysis of transistor breakdown was performed through computer simulations to understand effects on circuit power and performance. A ring oscillator circuit was utilized as a generic logic circuit for this research. The breakdown was modeled by resistors placed between the transistor terminals. The value of the resistor represents the severity of the breakdown; large resistors represent fresh transistors, whereas low resistors represent a fully broken transistor. In addition to computer simulations, real ICs were studied by taking power measurements experimentally. This research aims to offer better insight into the impact of transistor breakdown and to improve IC design in nano-scale. Through this internship program, the undergraduate students not only contributed to research and discovery, but also gained valuable experience and knowledge of nano-scale circuits that could have not been achieved in traditional educational methods.
利用暑期实习让本科生参与纳米电路研究
根据摩尔定律,半导体技术一直在稳步发展。目前的几代技术已经达到了远低于100纳米的尺寸,纳米级现象非常突出。在如此小的尺度上,晶体管的表现与大多数本科水平教科书中教授的经典长通道器件非常不同。此外,纳米级电路设计还面临着新的挑战,如工艺变化和可靠性问题,这些问题在本科课程中没有教授。研究最新技术问题的机会通常只提供给从事相关研究项目的研究生。为了解决这一差距,我们利用NASA课程改进合作伙伴奖(CIPAIR)的资助,创建了一个暑期实习项目,让社区大学生参与纳米级半导体技术中电路设计的最新挑战的研究项目。通过该项目,四名社区大学生在两名研究生的指导下进行了一项研究项目,分析了纳米尺度上晶体管老化效应导致的集成电路性能下降。在本研究中,通过计算机模拟来分析晶体管击穿对电路功率和性能的影响。本研究采用环形振荡电路作为通用逻辑电路。击穿是通过放置在晶体管端子之间的电阻来模拟的。电阻器的值表示击穿的严重程度;大的电阻代表新的晶体管,而小的电阻代表一个完全损坏的晶体管。除了计算机模拟外,还对实际集成电路进行了功率测量实验研究。本研究旨在更好地了解晶体管击穿的影响,并改进纳米级集成电路的设计。通过这个实习项目,本科生不仅为研究和发现做出了贡献,而且获得了传统教育方法无法获得的宝贵经验和知识。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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