A Highly Linear CMOS Down Conversion Double Balanced Mixer

Abstract

This paper presents a high linearity CMOS down conversion double balanced mixer for IEEE802.11/g Wireless LAN application with 2.4 GHz operating frequency. In this Gilbert type mixer design, various high linearity techniques have been incorporated such as current-reuse bleeding technique, common gate transconductance amplifier configuration and tuned loads techniques. All these techniques were combined into a single design and the comparison of this proposed mixer with the recent literature shows significant improvement in linearity parameters such as intermodulation (IMR3), third-order input intercept point (IIP3) and 1dB compression point without degrading other important parameters. The mixer structure is designed using TSMC 0.25 mum standard CMOS technology and is simulated using EldoRF simulator from Mentor Graphics environment. The mixer's simulated result shows the input intercept point (IIP3) of 12.810 dB, the intermodulation IMR3 of 129.816dB and the 1 dB compression point of 5.075 dB. The mixer operates at 1.8 V with 13.30 mW power consumption. Meanwhile, the measured conversion gain and noise figure of this double balanced mixer were -2.688 dB and 13.678 dB respectively.