Implementation of fast multiplier using modified Radix-4 booth algorithm with redundant binary adder for low energy applications

Abstract

The main objective of this paper is to implement a multiplier for high speed and low energy applications. Multipliers are the building blocks of high performance systems like FIR filters, Digital signal processors, etc in which speed is the dominating factor. There are many multiplier architectures developed to increase the speed of algebra. Booth algorithm is the most effective algorithm used for fast performances. This works by introducing a high performance multiplier using Modified Radix-4 booth algorithm with Redundant Binary Adder to get high speed. A comparative study of different booth algorithms in terms of power consumption, delay, area, energy and energy delay product is also discussed in this work. All the circuits are simulated in the Cadence simulation tool using 180nm technology. The experimental results show that the proposed booth multiplier shows high speed, low energy and low energy delay product compared to the existing booth multipliers.