{"title":"Performance Analysis of TMG FinFETs for Low Power Application with Improved Analog/RF Characteristics","authors":"Somya Saraswat, D. Yadav, Sachin Kumar, Nitish Parmar, Ritwik Sharma, Atul Kumar","doi":"10.1109/SCEECS48394.2020.103","DOIUrl":null,"url":null,"abstract":"In this manuscript, a 3D simulation model of FinFET is proposed. The device is designed in such a manner that the gate is made with three metals of different work functions, so it’s named as Tri-Metal Gate (TMG) FinFET. The work function at source/channel junction is kept high in comparison to the drain/channel junction to reduce DIBL and improve transconductance. This structure improves ONstate current, with suppressed OFF-state current. Further DC and analog/RF characteristics such as transfer characteristics, parasitic capacitance (Cgd, Cgs), transconductance (gm), cut off frequency (fT), output transconductance (gds), transconductance generation factor(TGF) are investigated. A comparative analysis of the proposed device with an existing device is also performed and results are studies. Above parameters support its utility at ultra-low power VLSI. The device has been simulated using TCAD simulator.","PeriodicalId":167175,"journal":{"name":"2020 IEEE International Students' Conference on Electrical,Electronics and Computer Science (SCEECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Students' Conference on Electrical,Electronics and Computer Science (SCEECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SCEECS48394.2020.103","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this manuscript, a 3D simulation model of FinFET is proposed. The device is designed in such a manner that the gate is made with three metals of different work functions, so it’s named as Tri-Metal Gate (TMG) FinFET. The work function at source/channel junction is kept high in comparison to the drain/channel junction to reduce DIBL and improve transconductance. This structure improves ONstate current, with suppressed OFF-state current. Further DC and analog/RF characteristics such as transfer characteristics, parasitic capacitance (Cgd, Cgs), transconductance (gm), cut off frequency (fT), output transconductance (gds), transconductance generation factor(TGF) are investigated. A comparative analysis of the proposed device with an existing device is also performed and results are studies. Above parameters support its utility at ultra-low power VLSI. The device has been simulated using TCAD simulator.