Wafer-mapping of hot carrier lifetime due to physical stress effects (MOSFET)

Abstract

It is pointed out that wafer-mapping of physical stresses by X-ray diffraction of a silicided CMOS process shows regions of both very high and low stress levels. The regions of high stress consistently have increased subthreshold slopes and are much more sensitive to hot-carrier induced threshold voltage shifts. Hot carrier lifetime variations over two orders of magnitude are explicitly shown to correlate with the physical stress level within a given highly stressed wafer. To optimally deliver maximum device performance with high reliability, it is essential that physical stress levels be measured, understood, and minimized.<>