A generic VHDL testbench to aid in development of board-level test programs

Abstract

This paper describes a generic VHDL testbench that has been developed to produce test vector information, including variable length cycles and strobe times. The test vector formats are appropriate for translation to several Automatic Test Systems (ATSs) for test. The testbench is created automatically using a tool developed by IITRI/RAC and the Rome Laboratory. The tool reads a VHDL structural model of a circuit board and generates the testbench. The testbench uses stimulus/response data captured in the IEEE Standard 1029.1, Waveform And Vector Exchange Specification (WAVES), format. Case examples for two different board models and two different ATSs are presented.<>