A novel ultra-low-power time-domain comparator based on subthreshold source-coupled logic

Abstract

This paper presents a novel approach for designing ultra-low power, low-voltage time-domain comparators using source-coupled logic (SCL) topology, operating in weak-inversion (subthreshold) regime (STSCL). The proposed time-domain comparator (TDC) is simulated in 0.18µm CMOS technology. Simulation results reveal that at low supply voltage of 0.5V, the comparator consumes only 0.8µW operating at 1.1MHz, with the accuracy of approximately 1mV.