Design-for-testability of the FLOVA

Abstract

This paper describes design-for-testability of the floating point digital signal processor, called FLOVA, which is based on VLIW architecture with 4 stage pipeline operation. Full-scan design, BIST (Built-In-Self-Test), and IEEE 1149.1 boundary-scan are applied to the flip-flops, the floating point processing units/the embedded memory units, and the I/O cells, respectively.