360-nm SOI process development for high-T applications in harsh environments

Abstract

Silicon-On-Insulator, SOI, is specially suited for radiation-hard, high-temperature, and high-frequency circuitry. The development of a 360-nm SOI fabrication process is presented. The minimum feature size is selected, as a compromise between ease of fabrication and to allow for the fabrication of RF circuits. The process flow, mask design, lithography, and dimensional characterization results are discussed. The target substrate is an SOI wafer with high resistivity base wafer. For the process development, e-beam lithography is used in all lithographic steps for flexibility. PMMA is used as positive resist, and SU-8 is used as negative resist. The die size is 500 μm × 500 μm. An EKV 2.6 MOSFET model for the developed process was created. The target is the fabrication of 3D integrated smart sensor for harsh environments, such as: on-engine, wheel mounted, and oil & gas production.