Critical analysis of 14nm device options

2011 International Conference on Simulation of Semiconductor Processes and Devices Pub Date : 2011-10-06 DOI:10.1109/SISPAD.2011.6035034

P. Oldiges, R. Muralidhar, P. Kulkarni, C. Lin, K. Xiu, D. Guo, M. Bajaj, N. Sathaye

引用次数: 7

Abstract

Modeling challenges and solutions for silicon based high performance device options at the 14nm node are presented. A variety of devices are being considered, using a variety of methods to analyze the devices objectively. Partially depleted silicon on insulator (PDSOI) devices are compared against extremely thin (ETSOI) and FinFET devices.

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14nm器件选项的关键分析

提出了14nm节点硅基高性能器件选项的建模挑战和解决方案。考虑到各种设备，使用各种方法客观地分析设备。部分耗尽绝缘体上硅(PDSOI)器件与极薄(ETSOI)和FinFET器件进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2011 International Conference on Simulation of Semiconductor Processes and Devices

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