A new full-adder design using XNOR-XOR circuit

Abstract

XNOR-XOR circuit is an essential part of many arithmetic circuits. In this seminal, proposed a 4T XNOR-XOR and 8T full-adder circuit. The proposed full-adder circuit designed by various logic styles is to be performed at an elaborated transistor-level to compare quantitatively and less number of transistor. The Simulation outcome demonstrates that the newly-proposed circuitry exhibit power consumption, less PDP and better performance in silicon area. These performances of all circuits are using the 90nm model parameter. Whole circuit simulation outcomes were obtained from TSPICE.