A Methodology for Placement of Regular and Structured Circuits

Abstract

Data path circuits are regular and best placed in bit-sliced pattern for improved Quality of Results such as timing, power, congestion and area. The cells in a column of bit slice structure are normally aligned on control pins or clock pins for straight routes, reducing power. The traditional way of placing data path circuits, using separate data path placer and then bringing them as macro in main design has its significant disadvantages. It is important for modern day placement tool to place random logic and data path circuits concurrently respecting the regularity that a data path circuit has by placing them in bit-sliced manner. It is not only important to place the data path elements in bit-sliced pattern but also that structure has to be maintained throughout the flow. The different set of optimization tricks can be applied to different bits of data path which can destroy the identical footprints of cells in column and that brings challenge of maintaining pin alignment. In addition to that, in lower nanometer nodes, fixed physical only cells pre-placed throughout the core area pose challenge of keeping bit-sliced structure intact. A flow for handling data path circuits in a place and route tool along with an algorithm for bit slice tiling is being proposed in this paper which addresses the challenges mentioned above.