A design of four-quadrant analog multiplier

Abstract

The paper proposes a new four-quadrant analog multiplier which consists of a multiplier cell, a mixed signal circuit and three signal subtraction circuits. Its advantages are: the design has single ended inputs; the geometry of all the transistors is equal; its output can be the product of two signal voltage, or the product of a signal current and a signal voltage. Simulation results are demonstrated by PSpice to confirm the operation of the circuit.