Simulated Annealing Applied to LUT-Based FPGA Technology Mapping

Abstract

Technology Mapping is one of the most important steps in the logic synthesis process, since it defines which set of logic elements will be used to implement the circuit in the target technology. This work proposes a mapping approach for Field Programmable Gate Arrays (FPGAs) based on the Simulated Annealing optimization technique to find an alternative solution to the problem. The utilization of Artificial Intelligence in Technology Mapping is promising because it strongly differs from existing algorithms due to the randomness factors in AI-based techniques. The developed approach acts on the mapping stage called coverage, aiming to minimize the number of K-cuts needed to map the complete logic of the circuit from the inputs to the outputs. Tests were performed in 85 benchmarks of the ISCAS85 and MCNC91 packages, widely known in the area and commonly used for performance testing of new approaches. The tests conducted found solutions comparable in several cases to the ABC tool, considered state-of-the-art in the Technology Mapping process, and even superior in some benchmarks, achieving improvements over ABC's results in approximately 19% of the evaluated benchmarks with K = 4 and 26% with K = 5.