A new method to estimate phases of sinusoidal jitter to evaluate high-speed links

Abstract

Analysis of high-speed links requires modeling of timing noise in devices and clock architecture as well as passive inter-connections. With the increased demand on data rate and low power in mobile devices such as 3D PoP, it is more challenging to predict bit error rate (BER) due to their tighten timing and voltage constraints. Phase relationship among different jitter sources becomes a key player deciding how well links perform. A new method based on the subspace concept is proposed to estimate the phases in multi-tone jitter sequences. Its accuracy is much less sensitive to the size of data than FFT based method. For the first time, the phase of one on-chip jitter sensitivity function is characterized out using limited data from measurement.