A test generation method for sequential circuits based on maximum utilization of internal states

Abstract

This paper presents a novel deterministic test pattern generation method for sequential circuits. The proposed method has several advantages over conventional methods, particularly in its maximum utilization of internal states. Such utilization permits shorter computational time, reduced test pattern length and fewer timing problems. In this method, the type of fault targeted for the next pattern generation is that which, on the basis of the current internal state of the circuit, is determined to be the easiest type to detect, and during pattern generation, the only value transitions traced are those which are necessary for a particular fault's detection. Experimental results show the proposed method to be efficient.