Performance comparison and analysis by electrical measurement for through-silicon vias (TSV) in wafer level package

Abstract

A low cost and high density through-silicon vias (TSV) on high resistivity silicon (HR-Si) wafer is presented. By skip of isolation layer between TSV and HR-Si wafer, the proposed TSV provides higher via density and resolves polymer residual at the bottom of TSV. To ensure electrical performance of proposed TSV, a series of test items such as transmission line, 3D inductor and TSV chain are designed and fabricated on HR-Si wafer. The electrical performance is compared to original TSV that has isolation layer between TSV and HR-Si wafer by measurement approach. Measurement results show TSV w/o isolation has even better performance as compared to TSV with isolation on the inductor's quality factor, transmission line loss and harmonics characteristic.