RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference

Abstract

RRAM-based computing-in-memory (CIM) can potentially improve the energy- and area-efficiency for AI edge processors, yet may still suffer from performance degradations due to the large DC current and parasitic capacitance in the cell array during computation. In this work, we propose a new CIM design leveraging the transient-charge-transferring (TCT) between the parasitic capacitors in the high-density foundry-compatible two-transistor-two-resistor (2T2R) RRAM array, which can perform DC-current-free multiply-and-accumulate (MAC) operations with improved energy-efficiency, reduced latency and enhanced signal margin. The concept of TCT-CIM is silicon demonstrated using a 180nm 400Kb RRAM test-chip, which has achieved 7.36 times power reduction compared to the conventional scheme and measured read access time less than 17.22 ns.