Advanced Package FAB Solutions(APFS) for Chiplet Integration

Abstract

For HPC applications, 2.5D and 3D technologies are employed for cloud, AI and ML. High-performance chip size continues to increase up to one reticle size and the cost of the leading-edge silicon node is recently soaring. This makes various solutions, such as MCM, 2.5D and 3D, necessary to develop fine pitch interconnection evolutions with hybrid Cu bonding or fine pitch microbump bonding processes. In this paper, the above mentioned Advanced Package FAB Solutions (APFS) will be introduced and discussed in terms of challenges and opportunities for emerging high-end computing and mobile processor platforms. Additionally, Fanout PKG, RDL interposer, high-performance 3D SIP and Integrated Stacked Capacitor (ISC) will also be introduced.