Transistor sizing and gate sizing using geometric programming considering delay minimization

Abstract

A comparison between gate sizing and transistor sizing to analyze the trade-off between execution time and minimum delay achieved is presented in this work. The transistor and gate sizing tools are based on Geometric Programming (GP) and delay is calculated using the Elmore delay model. Tests were made mapping ISCAS'85 benchmark circuits for 45nm technology considering delay minimization. First, circuits were mapped to a typical standard cell library. Then, the gate sizing and transistor sizing were performed. Gate sizing reduced the delay by 21%, in average, for a same area and power values of the sizing provided by standard-cells library. After transistor sizing reduced delay by 40.4% and power consumption by 2.9%, in average, compared with gate sizing. However, transistor sizing requires a bigger computing time, using a number of variables twice higher than with gate sizing.